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Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths
March 17-March 19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISQED.2008.869th International Symposium on Qualit ...
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It is expected that the soft error rate (SER) of combinational logic will increase significantly. Previous solutions to mitigate soft errors in combinational logic suffer from delay penalty or area/power overhead. In this paper, we proposed an output remapping technique to reduce SER of critical paths. Experimental results show up to about 20X increase in Qcritical. So the SER is reduced significantly. This method does not introduce any delay penalty. The area/power overhead is limited as well. The output remapping method is based on our novel glitch width model. The analysis shows that output remapping technique works well along with technology scaling.
Citation:
Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, "Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths," isqed, pp.74-77, 9th International Symposium on Quality Electronic Design (isqed 2008), 2008
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