Balancing System Level Pipelines with Stage Voltage Scaling

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.20

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	Hui Guo, Sri Parameswaran, "Balancing System Level Pipelines with Stage Voltage Scaling," VLSI, IEEE Computer Society Annual Symposium on, pp. 287-289, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.20, author = {Hui Guo and Sri Parameswaran}, title = {Balancing System Level Pipelines with Stage Voltage Scaling}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {287-289}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.20}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Balancing System Level Pipelines with Stage Voltage Scaling SN - 0-7695-2365-X SP287 EP289 A1 - Hui Guo, A1 - Sri Parameswaran, PY - 2005 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Hui Guo, University of New South Wales

Sri Parameswaran, University of New South Wales

This paper presents an approach to dynamically balance the pipeline by scaling the stage supply voltages. Simulation results show that by such an approach about 50% improvement in throughput and response time, and 11% improvement in power consumption can be achieved with limited memory overhead.

Citation:

Hui Guo, Sri Parameswaran, "Balancing System Level Pipelines with Stage Voltage Scaling," isvlsi, pp.287-289, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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