CMOS Realization of Online Testable Reversible Logic Gates

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.23

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	ASCII Text	x
	D. P. Vasudevan, P. K. Lala, J. P. Parkerson, "CMOS Realization of Online Testable Reversible Logic Gates," VLSI, IEEE Computer Society Annual Symposium on, pp. 309-310, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.

	BibTex	x
	@article{ 10.1109/ISVLSI.2005.23, author = {D. P. Vasudevan and P. K. Lala and J. P. Parkerson}, title = {CMOS Realization of Online Testable Reversible Logic Gates}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2005}, isbn = {0-7695-2365-X}, pages = {309-310}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.23}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - CMOS Realization of Online Testable Reversible Logic Gates SN - 0-7695-2365-X SP309 EP310 A1 - D. P. Vasudevan, A1 - P. K. Lala, A1 - J. P. Parkerson, PY - 2005 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

D. P. Vasudevan, University of Arkansas

P. K. Lala, University of Arkansas

J. P. Parkerson, University of Arkansas

Three reversible logic gates that can be used to implement reversible digital circuits with various levels of complexity are proposed. The major feature of these gates is that they provide online-testability for circuits implemented using them. The CMOS realization of these gates is presented in this paper.

Citation:

D. P. Vasudevan, P. K. Lala, J. P. Parkerson, "CMOS Realization of Online Testable Reversible Logic Gates," isvlsi, pp.309-310, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005

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