Timing jitter in long on-chip interconnects has become an increasingly important issue in signal integrity and timing violations. In this paper, we focus on cycle-to-cycle jitter induced by repeater power supply noise in both point-to-point and branched RC and RLC interconnects in 70nm CMOS. We develop an analytical expression for jitter based on propagation delay variation that accurately predicts HSPICE simulation results. We show the difference in impact between RC and RLC wire models on jitter (up to 64%). We also show a method for jitter-optimal repeater insertion which differs from conventional delay optimal insertion methods, resulting in larger repeaters. Finally, we introduce methods which can decrease timing violations in branched global interconnects by adjusting repeater size and tuning the phase of the power supply noise.