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On Reducing Peak Current and Power during Test
Tampa, Florida May 11-May 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.53IEEE Computer Society Annual Symposiu ...
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Wei Li, University of Iowa
Sudhakar M. Reddy, University of Iowa
Irith Pomeranz, Purdue University
This paper presents a Progressive Match Filling (PMF) technique to reduce the peak current and power dissipation during the fast capture cycle in broadside delay fault testing. The proposed method fills the unspecified values (X) in the generated initialization vector such that the resulting launch vector at a minimal Hamming distance from the initialization vector. The proposed method does not require any hardware modification and can be used to obtain any test sets that require two pattern tests. Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISCAS 89 circuits.
Citation:
Wei Li, Sudhakar M. Reddy, Irith Pomeranz, "On Reducing Peak Current and Power during Test," isvlsi, pp.156-161, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005
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