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Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses
Tampa, Florida May 11-May 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.56IEEE Computer Society Annual Symposiu ...
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Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin, "Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses," VLSI, IEEE Computer Society Annual Symposium on, pp. 268-269, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.
 
 
BibTex
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@article{ 10.1109/ISVLSI.2005.56,
author = {Bertrand Le Gal and Emmanuel Casseau and Sylvain Huet and Eric Martin},
title = {Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses},
journal ={VLSI, IEEE Computer Society Annual Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2365-X},
pages = {268-269},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.56},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI, IEEE Computer Society Annual Symposium on
TI - Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses
SN - 0-7695-2365-X
SP268
EP269
A1 - Bertrand Le Gal,
A1 - Emmanuel Casseau,
A1 - Sylvain Huet,
A1 - Eric Martin,
PY - 2005
KW - null
VL - 0
JA - VLSI, IEEE Computer Society Annual Symposium on
ER -
 
Bertrand Le Gal, University of South Brittany
Emmanuel Casseau, University of South Brittany
Sylvain Huet, University of South Brittany
Eric Martin, University of South Brittany
Multimedia applications are often characterized by a large number of data accesses with regular and periodic access patterns. In these cases, optimized pipelined memory access controllers can be generated improving the pipeline access mode to RAM. We focus on the design and the implementation of memory sequencers that can be automatically generated from a behavioral synthesis tool and which can efficiently handle predictable address patterns as well as unpredictable ones (dynamic address computations) in a pipeline way.
Citation:
Bertrand Le Gal, Emmanuel Casseau, Sylvain Huet, Eric Martin, "Pipelined Memory Controllers for DSP Applications Handling Unpredictable Data Accesses," isvlsi, pp.268-269, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005
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