Rotary clock is a multi-gigahertz clock distribution technique based on the principle of wave propagation in transmission lines. In this paper, we perform the first quantitative investigation on the power dissipation of rotary clock designs. Specifically, we have developed a software tool based on the method of partial element equivalent circuit (PEEC) that is capable of extracting the SPICE netlist from a layout specification of a rotary clock design. As a result, we are able to accurately estimate the frequency and power dissipation of the rotary clock design using SPICE simulations. Using our tool, we have uncovered the key power dissipation mechanisms of rotary clock and proposed several power reduction strategies. Furthermore, our power analysis has revealed that rotary clock designs can achieve power savings of up to 70% in comparison with conventional clock tree implementations.