Interconnect congestion estimation plays an important role in the physical design of integrated circuits. This paper presents a novel probabilistic approach to predicting wiring space in two-dimensional arrays. We propose a hierarchical estimation method to derive approximated upper bounds for wiring space. We use the net density distribution for predicting the routing congestion. Experimental results demonstrate the promising performance of the new approach.
Citation:
Fei He, Xiaoyu Song, Lerong Cheng, Guowu Yang, Zhiwei Tang, Ming Gu, Jiaguang Sun, "A Hierachical Method for Wiring and Congestion Prediction," isvlsi, pp.307-308, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005