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Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator
Tampa, Florida May 11-May 12
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.61IEEE Computer Society Annual Symposiu ...
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A. Maili, C. Steger, R. Wei?, R. Quigley, D. Dalton, "Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator," VLSI, IEEE Computer Society Annual Symposium on, pp. 290-291, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005.
 
 
BibTex
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@article{ 10.1109/ISVLSI.2005.61,
author = {A. Maili and C. Steger and R. Wei? and R. Quigley and D. Dalton},
title = {Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator},
journal ={VLSI, IEEE Computer Society Annual Symposium on},
volume = {0},
year = {2005},
isbn = {0-7695-2365-X},
pages = {290-291},
doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2005.61},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI, IEEE Computer Society Annual Symposium on
TI - Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator
SN - 0-7695-2365-X
SP290
EP291
A1 - A. Maili,
A1 - C. Steger,
A1 - R. Wei?,
A1 - R. Quigley,
A1 - D. Dalton,
PY - 2005
KW - null
VL - 0
JA - VLSI, IEEE Computer Society Annual Symposium on
ER -
 
A. Maili, Graz University of Technology
C. Steger, Graz University of Technology
R. Wei?, Graz University of Technology
R. Quigley, University College Dublin
D. Dalton, University College Dublin
This paper presents a hardware acceleration system based on a gate-level accelerator and an on-chip micro-processor enabling co-simulation of C-models with gate-level modules on the accelerator. This solution tackles the communication bottleneck that occurs when using hardware accelerators or emulators to speed up simulation. We analyze this bottleneck for the APPLES gate-level hardware accelerator and present the speedup that can be achieved by a prototype of the PowerPC-APPLES accelerator implemented on a Virtex2Pro FPGA on a PCI card.
Citation:
A. Maili, C. Steger, R. Wei?, R. Quigley, D. Dalton, "Reducing the Communication Bottleneck via On-Chip Cosimulation of Gate-Level HDL and C-Models on a Hardware Accelerator," isvlsi, pp.290-291, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005
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