Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuitively believe that multiple oxide thickness may be useful to reduce the direct tunneling current dissipation. Since no foundry design rules are available for design and layout using technology below 90nm we provide analytical models to calculate the tunneling current and the propagation delay of behavioral level components. We then characterize those components for 45nm technology and provide an algorithm for scheduling of datapath operations such that the overall tunneling power dissipation of the circuit is minimal. We have carried out extensive experiments for various behavioral level benchmarks under various constraints and observed significant reductions.