In this paper, we present the design and evaluation of a two-phase resonant clock generation and distribution system with layout-extracted inductor parameters in a 0.13?m copper process. The design includes a programmable replenishing clock generator and tunable capacitors that enable the exploration of skew, jitter, and clock amplitude. Our simulation results show that worst-case skew is within 8.5% of clock period in the range of 790MHz to 1.22GHz under a variety of load imbalance conditions. Furthermore, energy dissipation is at least 60% lower than conventional square waveform distribution.
Citation:
Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler, "Two-Phase Resonant Clock Distribution," isvlsi, pp.65-70, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05), 2005