A Parallel Architecture for Hardware Face Detection

Karlsruhe, Germany March 02-March 03

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.10

IEEE Computer Society Annual Symposiu ...

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	T. Theocharides, N. Vijaykrishnan, M. J. Irwin, "A Parallel Architecture for Hardware Face Detection," VLSI, IEEE Computer Society Annual Symposium on, pp. 452-453, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.10, author = {T. Theocharides and N. Vijaykrishnan and M. J. Irwin}, title = {A Parallel Architecture for Hardware Face Detection}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {452-453}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.10}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A Parallel Architecture for Hardware Face Detection SN - 0-7695-2533-4 SP452 EP453 A1 - T. Theocharides, A1 - N. Vijaykrishnan, A1 - M. J. Irwin, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

T. Theocharides, University of Cyprus

N. Vijaykrishnan, Penn State University

M. J. Irwin, Penn State University

Face detection is a very important application in the field of machine vision. In this paper, we present a scalable parallel architecture which performs face detection using the AdaBoost algorithm. Experimental results show that the proposed architecture can detect faces with the same accuracy as the software implementation, on real-time video at a frame rate of 52 frames per second.

Citation:

T. Theocharides, N. Vijaykrishnan, M. J. Irwin, "A Parallel Architecture for Hardware Face Detection," isvlsi, pp.452-453, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

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