An Optimized BIST Architecture for FPGA Look-Up Table Testing

Karlsruhe, Germany March 02-March 03

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.24

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	Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi, "An Optimized BIST Architecture for FPGA Look-Up Table Testing," VLSI, IEEE Computer Society Annual Symposium on, pp. 420-421, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.24, author = {Mahnaz Sadoughi Yarandi and Armin Alaghi and Zainalabedin Navabi}, title = {An Optimized BIST Architecture for FPGA Look-Up Table Testing}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {420-421}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.24}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - An Optimized BIST Architecture for FPGA Look-Up Table Testing SN - 0-7695-2533-4 SP420 EP421 A1 - Mahnaz Sadoughi Yarandi, A1 - Armin Alaghi, A1 - Zainalabedin Navabi, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Mahnaz Sadoughi Yarandi, University of Tehran, Tehran, Iran

Armin Alaghi, University of Tehran, Tehran, Iran

Zainalabedin Navabi, University of Tehran, Tehran, Iran

This paper presents a complete BIST architecture for FPGA Look-Up Tables. This architecture can detect multiple faults, and can be configured to detect a fault in as few as five LUTs. Unlike an earlier work, our method places the Output Response Analyzer (ORA) within the FPGA.

Citation:

Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi, "An Optimized BIST Architecture for FPGA Look-Up Table Testing," isvlsi, pp.420-421, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

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