High performance service-time-stamp computation for WFQ IP packet scheduling

Karlsruhe, Germany March 02-March 03

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.49

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	C. McKillen, S. Sezer, Xin Yang, "High performance service-time-stamp computation for WFQ IP packet scheduling," VLSI, IEEE Computer Society Annual Symposium on, pp. 65-70, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.49, author = {C. McKillen and S. Sezer and Xin Yang}, title = {High performance service-time-stamp computation for WFQ IP packet scheduling}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {65-70}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.49}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - High performance service-time-stamp computation for WFQ IP packet scheduling SN - 0-7695-2533-4 SP65 EP70 A1 - C. McKillen, A1 - S. Sezer, A1 - Xin Yang, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

C. McKillen, Institute of Electronics, Communications and Information Technology

S. Sezer, Institute of Electronics, Communications and Information Technology

Xin Yang, Institute of Electronics, Communications and Information Technology

In this paper the design and implementation of a unique service-time-stamp computation circuit, called the finishing tag, for WFQ based packet scheduling is presented. The implementation is based on UMC 130nm standard cell technology, and placed and routed using Cadence SoC encounter. The design targets the development of programmable IP packet scheduling circuits for next generation network processing platforms for line-rates beyond 200Gbps.

Citation:

C. McKillen, S. Sezer, Xin Yang, "High performance service-time-stamp computation for WFQ IP packet scheduling," isvlsi, pp.65-70, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

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