High-Performance Noise-Robust Asynchronous Circuits

Karlsruhe, Germany March 02-March 03

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.51

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	Pankaj Golani, Peter A. Beerel, "High-Performance Noise-Robust Asynchronous Circuits," VLSI, IEEE Computer Society Annual Symposium on, pp. 173-178, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.51, author = {Pankaj Golani and Peter A. Beerel}, title = {High-Performance Noise-Robust Asynchronous Circuits}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {173-178}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.51}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - High-Performance Noise-Robust Asynchronous Circuits SN - 0-7695-2533-4 SP173 EP178 A1 - Pankaj Golani, A1 - Peter A. Beerel, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Pankaj Golani, University of Southern California, Los Angeles

Peter A. Beerel, University of Southern California, Los Angeles

This paper presents the development of a prototype highperformance asynchronous standard-cell library based on the static single-track full buffer family. It focuses on the design choices and challenges that mitigate sensitiveness to noise, including transistor sizing and wire spacing rules. Post-layout simulation results demonstrate its robustness to noise while achieving a peak cycle time of 5.7 FO4 delays.

Citation:

Pankaj Golani, Peter A. Beerel, "High-Performance Noise-Robust Asynchronous Circuits," isvlsi, pp.173-178, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

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