Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors

Karlsruhe, Germany March 02-March 03

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.69

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	Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi, "Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors," VLSI, IEEE Computer Society Annual Symposium on, pp. 193-198, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.69, author = {Masanori Hariyama and Michitaka Kameyama and Yasuhiro Kobayashi}, title = {Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {193-198}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.69}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors SN - 0-7695-2533-4 SP193 EP198 A1 - Masanori Hariyama, A1 - Michitaka Kameyama, A1 - Yasuhiro Kobayashi, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Masanori Hariyama, Tohoku University, Japan

Michitaka Kameyama, Tohoku University, Japan

Yasuhiro Kobayashi, Oyama National College of Technology, Japan

One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design methodology for a logic-in-memory architecture where each of memory modules is connected to its dedicated processing element(PE). An efficient memory allocation to minimize the number of memory modules and PEs under a time constraint is proposed based on regularity.

Citation:

Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi, "Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors," isvlsi, pp.193-198, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

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