A New Protocol Stack Model for Network on Chip

Karlsruhe, Germany March 02-March 03

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.7

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	Masood Dehyadgari, Mohsen Nickray, Ali Afzali-kusha, Zainalabedin Navabi, "A New Protocol Stack Model for Network on Chip," VLSI, IEEE Computer Society Annual Symposium on, pp. 440-441, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006.

	BibTex	x
	@article{ 10.1109/ISVLSI.2006.7, author = {Masood Dehyadgari and Mohsen Nickray and Ali Afzali-kusha and Zainalabedin Navabi}, title = {A New Protocol Stack Model for Network on Chip}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2006}, isbn = {0-7695-2533-4}, pages = {440-441}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2006.7}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - A New Protocol Stack Model for Network on Chip SN - 0-7695-2533-4 SP440 EP441 A1 - Masood Dehyadgari, A1 - Mohsen Nickray, A1 - Ali Afzali-kusha, A1 - Zainalabedin Navabi, PY - 2006 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Masood Dehyadgari, University of Tehran, Iran

Mohsen Nickray, University of Tehran, Iran

Ali Afzali-kusha, University of Tehran, Iran

Zainalabedin Navabi, Northeastern University

In this paper, we present a communication protocol for Network on Chip architectures which have complex packet switched communication protocols. In order to manage this complexity and advance reusability, a layered approach is taken. It is a 4-layered protocol stack including application, transaction, data-link and physical layers. Our protocol stack supports the best effort traffic as well as guaranteed bandwidth using the virtual channels which logically share the physical links. In order to evaluate the design, a HDL implementation of this protocol stack is implemented and synthesized. The results show 0.5% of a Virtex II 2VP30 FPGA is employed by our proposed protocol stack for each resource network interface.

Citation:

Masood Dehyadgari, Mohsen Nickray, Ali Afzali-kusha, Zainalabedin Navabi, "A New Protocol Stack Model for Network on Chip," isvlsi, pp.440-441, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006

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