We present a routing-tree construction algorithm that considers multi-objectives of performance, power and congestion concurrently. Congestion is measured with balanced usage of routing resources among layers. Simultaneous buffer insertion and layer assignment tends to produce routing-trees with shorter overall length. Applying the proposed simultaneous algorithm on a subset of routes on a commercial 64-bit microprocessor yielded 9% less repeater usage and 1.5% shorter overall routingtree length with improved overall performance at the same time, compared to sequential routing-tree construction approach.
Citation:
Cengiz Alkan, Tom Chen, "Routing-Tree Construction with Concurrent Performance, Power and Congestion Optimization," isvlsi, pp.367-372, IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006