In this paper, the design techniques and considerations for each building block required for analog signal processing in HD-DVD PRML read channel are presented and the procedures of analog signal processing are also described. The Analog Front-End Circuitry (AFE) includes the circuits of RF Summer Attenuator Equalizer AGC and ADC. The Equalizer is constructed by seven-pole two-zero 0.05 degree equiripple linear phase Gm-C filter. It has a cutoff frequency (fc) tunable between 8 and 39MHz and it is also able to provide up to 12dB of boost at fc. The constant group delay bandwidth of the filter is 1.65 fc. And the AGC circuit which uses the exponential type of VGA can has nearly constant settling time within 10us and it has 1Vpp constant amplitude output. Behind the AGC is the flash ADC, it has a resolution of 6 bit and 300MHz conversion rate and it is enough to provide the digital data required for the digital part which uses the method of partial response maximum likelihood (PRML). The design was made using TSMC 0.35um 2P4M mixed-signal CMOS process. The AFE consumes 520 mW from a single 3.3v power supply, and occupies an area of 12.8m m ^2 .