In traditional floorplanners, the lack of information about timing schedule from high level synthesis (HLS) often leads to the failure or iterations of timing schedule design. In this paper, timing analysis with interconnect delay is introduced to the process of floorplanning, which enables the timing schedule information considered in physical design. Furthermore, based on timing schedule information, the timing slacks along data paths are used to optimize the interconnect power consumptions. Without violating timing specification, we propose a delay budget method to distribute the slacks along interconnects in order to optimize the total interconnect power. Experimental results show that our interconnect power optimization method based on timing analysis can optimize the packing to meet the cycle time requirement effectively and save the interconnect power consumption about 13.2% on average.