Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder

Porto Alegre, Brazil March 09-March 11

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http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.64

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	Bruno Zatt, Arnaldo Azevedo, Luciano Agostini, Altamiro Susin, Sergio Bampi, "Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder," VLSI, IEEE Computer Society Annual Symposium on, pp. 445-446, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007.

	BibTex	x
	@article{ 10.1109/ISVLSI.2007.64, author = {Bruno Zatt and Arnaldo Azevedo and Luciano Agostini and Altamiro Susin and Sergio Bampi}, title = {Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder}, journal ={VLSI, IEEE Computer Society Annual Symposium on}, volume = {0}, year = {2007}, isbn = {0-7695-2896-1}, pages = {445-446}, doi = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.64}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI, IEEE Computer Society Annual Symposium on TI - Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder SN - 0-7695-2896-1 SP445 EP446 A1 - Bruno Zatt, A1 - Arnaldo Azevedo, A1 - Luciano Agostini, A1 - Altamiro Susin, A1 - Sergio Bampi, PY - 2007 KW - null VL - 0 JA - VLSI, IEEE Computer Society Annual Symposium on ER -

Bruno Zatt, UFRGS - Porto Alegre, RS, Brazil

Arnaldo Azevedo, UFRGS - Porto Alegre, RS, Brazil

Luciano Agostini, UFRGS - Porto Alegre, RS, Brazil

Altamiro Susin, UFRGS - Porto Alegre, RS, Brazil

Sergio Bampi, UFRGS - Porto Alegre, RS, Brazil

This paper presents a motion compensation memory hierarchy for an H.264/AVC decoder with support to bi-predictive frames. The designed memory hierarchy reduces the memory bandwidth through the use of a three-dimensional cache and through the use of extra memory saving techniques. The cache size parameters were determined through the evaluation of simulation results from real video sequences. The designed memory hierarchy provides, in average, a 60% of bandwidth reduction. The architecture was designed in VHDL and synthesized for a Xilinx Virtex-II PRO FPGA.

Citation:

Bruno Zatt, Arnaldo Azevedo, Luciano Agostini, Altamiro Susin, Sergio Bampi, "Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder," isvlsi, pp.445-446, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07), 2007

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