We investigate how to apply power-gating techniques to logic circuits for maximal total power reduction. We compare techniques that employ overdriven low-Vt power switches (SCCMOS) with those employing high-Vt power switches (MTCMOS). When sized under the same constraints for maximum voltage drop in active mode, MTCMOS has 10% shorter total wake-up time compared to SCCMOS. However, SCCMOS performs better in saving power than MTCMOS as logic circuit blocks increase in size and have increasing lengths of idle time. To obtain maximal power savings in idle mode, we introduce a process variation tolerant control circuit for overdrive voltage generators that offers a 2.7? power savings improvement for a 130-nm process.