Xilinx Virtex-II / Virtex-II Pro FPGAs provide the possibility of partial and dynamic run-time reconfiguration. This feature can be used in adaptive systems providing the possibility to adapt to application requirements by exchanging parts of the hardware while other parts stay operative. This computing in time and space and many other fine grained adjustments within the architectures, opens new dimensions for electronic system design as well as for novel scheduling mechanisms based on well established graph-based algorithms in comparison to pure microprocessor based electronic systems. However, at the moment it is not possible to visualize the physical configuration of the chip and the manifold possibilities of manipulations on the device. This feature allows to demonstrate the system?s behavior and helps to debug final integrated reconfigurable systems. This paper presents an approach to the system integration of an autonomously working on-line visualization stand alone IP-Core integrated on Xilinx Virtex-II and Virtex-II Pro FPGAs.