Negative bias temperature instability (NBTI) has become a growing concern in nanometer technologies. It may re- duce the lifetime of reliable operation of PMOS transistors in the design. Process variation has started impacting the nanometer ICs by reducing the parametric yield. Process variation together with NBTI can further reduce the reli- able lifetime of ICs. Conventional ASIC design methodol- ogy uses pre-characterized standard cells to optimize the design as per specifications. The standard cells occupy nearly 75% of the chip real estate in a sea-of-gate design. Therefore process variation and NBTI tolerant robust stan- dard cells may help in reducing the margin of performance variation thereby increasing the lifetime of reliable opera- tion. The use of robust cells may further help in reducing the design time overhead. In this work, we model the com- bined effect of process variation and NBTI on intrinsic gate delay using a reduced dimension modeling technique. We use the models to optimize the standard cells in the pres- ence of NBTI and process variations with a target lifetime of 10 years. Experimental results show that the use of op- timized robust standard cells can considerably improve the tolerance of circuit in the self-timed sections of critical tim- ing paths.