A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs

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http://doi.ieeecomputersociety.org/10.1109/ITC.2004.10

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	Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi, "A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs," Test Conference, International, pp. 1108-1117, International Test Conference 2004 (ITC'04), 2004.

	BibTex	x
	@article{ 10.1109/ITC.2004.10, author = {Bhaskar Chatterjee and Manoj Sachdev and Ali Keshavarzi}, title = {A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs}, journal ={Test Conference, International}, volume = {0}, year = {2004}, issn = {1089-3539}, pages = {1108-1117}, doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.10}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs SN - 1089-3539 SP1108 EP1117 A1 - Bhaskar Chatterjee, A1 - Manoj Sachdev, A1 - Ali Keshavarzi, PY - 2004 KW - null VL - 0 JA - Test Conference, International ER -

Bhaskar Chatterjee, University of Waterloo, Waterloo, ON, Canada

Manoj Sachdev, University of Waterloo, Waterloo, ON, Canada

Ali Keshavarzi, Circuits Research, Intel Labs Hillsboro, OR, USA

Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. This has resulted in the design of multi-gigahertz microprocessors with unprecedented levels of integration. However, this is posing serious challenges to IC testing and long-term reliability. A major source of failures and test escapes in high performance ICs can be attributed to timing-only parametric failures. In this paper, we implement a DFT technique to detect delay faults in a full custom 32-bit high performance ALU. We present the energy-delay tradeoffs and scaling trends associated with our DFT technique for the 180nm-65nm CMOS technologies. In addition, we demonstrate how this technique can be used to detect delay faults with improved resolution (~60ps for 180nm technology) at relatively low, test mode clock frequencies.

Citation:

Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi, "A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs," itc, pp.1108-1117, International Test Conference 2004 (ITC'04), 2004

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