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Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors
Charlotte, NC, USA October 26-October 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.100International Test Conference 2004 (I ...
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Kendrick Baker, Raytheon Company, Plano, TX
Mehrdad Nourani, University of Texas at Dallas, Richardson, TX
This paper presents a method of creating a true/complement pattern set of optimal size that satisfies simultaneous switching limit constraints. This method is an improvement over previous methods in that it has better runtime characteristics as well as the ability to handle additional scenarios. It can produce safe initial vectors, produce vectors that consider switching limits by device rather than globally, and reduce (or eliminate) the number of morph vectors required.
Citation:
Kendrick Baker, Mehrdad Nourani, "Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors," itc, pp.163-172, International Test Conference 2004 (ITC'04), 2004
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