Growing ASIC design sizes and advanced deep submicron technologies require new fault models and more test vectors to meet high test quality goals. To realize these goals within given test resources and cost constraints, new DFT techniques must be used. This paper reports test quality metrics and the test cost of industrial designs for different fault models using three DFT techniques: ATPG for deterministic patterns, Logic BIST for pseudo-random patterns, and EDT for compressed deterministic patterns. It is shown how these techniques can be used to achieve the high quality goals within the test resources currently available for stuck-at tests.