A Holistic Parallel and Hierarchical Approach towards Design-For-Test

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http://doi.ieeecomputersociety.org/10.1109/ITC.2004.15

International Test Conference 2004 (I ...

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	C. P. Ravikumar, G. Hetherington, "A Holistic Parallel and Hierarchical Approach towards Design-For-Test," Test Conference, International, pp. 345-354, International Test Conference 2004 (ITC'04), 2004.

	BibTex	x
	@article{ 10.1109/ITC.2004.15, author = {C. P. Ravikumar and G. Hetherington}, title = {A Holistic Parallel and Hierarchical Approach towards Design-For-Test}, journal ={Test Conference, International}, volume = {0}, year = {2004}, issn = {1089-3539}, pages = {345-354}, doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.15}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Test Conference, International TI - A Holistic Parallel and Hierarchical Approach towards Design-For-Test SN - 1089-3539 SP345 EP354 A1 - C. P. Ravikumar, A1 - G. Hetherington, PY - 2004 KW - Experiments and Case Studies KW - Practical Test Engineering VL - 0 JA - Test Conference, International ER -

C. P. Ravikumar, Texas Instrument (India)

G. Hetherington, Texas Instrument Ltd, United Kingdom

While design-for-test methods such as scan, ATPG, and memory BIST are now well established for ASIC products, their run-time for multi-million gate designs has become a problem. Too often, a tape-out is held up because pattern generation and verification are incomplete. This paper describes a holistic design-for-test approach which exploits both hierarchy and parallelism on every aspect of the DFT to minimize the run-time impact.

Index Terms:

Experiments and Case Studies, Practical Test Engineering

Citation:

C. P. Ravikumar, G. Hetherington, "A Holistic Parallel and Hierarchical Approach towards Design-For-Test," itc, pp.345-354, International Test Conference 2004 (ITC'04), 2004

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