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Simulation Based System Level Fault Insertion Using Co-verification Tools
Charlotte, NC, USA October 26-October 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.161International Test Conference 2004 (I ...
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Bill Eklow, Anoosh Hosseini, Chi Khuong, Shyam Pullela, Toai Vo, Hien Chau, "Simulation Based System Level Fault Insertion Using Co-verification Tools," Test Conference, International, pp. 704-710, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.161,
author = {Bill Eklow and Anoosh Hosseini and Chi Khuong and Shyam Pullela and Toai Vo and Hien Chau},
title = {Simulation Based System Level Fault Insertion Using Co-verification Tools},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {704-710},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.161},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - Simulation Based System Level Fault Insertion Using Co-verification Tools
SN - 1089-3539
SP704
EP710
A1 - Bill Eklow,
A1 - Anoosh Hosseini,
A1 - Chi Khuong,
A1 - Shyam Pullela,
A1 - Toai Vo,
A1 - Hien Chau,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Bill Eklow, Cisco Systems Inc., San Jose CA,
Anoosh Hosseini, Cisco Systems Inc., San Jose CA,
Chi Khuong, Cisco Systems Inc., San Jose CA,
Shyam Pullela, Cisco Systems Inc., San Jose CA
Toai Vo, Cisco Systems Inc., San Jose CA
Hien Chau, Cisco Systems Inc., San Jose CA
This paper presents a simulation-based, fault insertion environment, which allows faults to be "injected" into a Verilog model of the hardware. A co-verification platform is used to allow real, system level software to be executed in the simulation environment. A fault manager is used to keep track of the faults that are inserted on to the hardware and to monitor diagnostic messages to determine whether the software is able to detect, diagnose and/or cope with the injected fault. Examples will be provided to demonstrate the capabilities of this approach as well as the resource requirements (time, system, human). Other benefits and issues of this approach will also be discussed.
Citation:
Bill Eklow, Anoosh Hosseini, Chi Khuong, Shyam Pullela, Toai Vo, Hien Chau, "Simulation Based System Level Fault Insertion Using Co-verification Tools," itc, pp.704-710, International Test Conference 2004 (ITC'04), 2004
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