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AC IO Loopback Design for High Speed uProcessor IO Test
Charlotte, NC, USA October 26-October 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.22International Test Conference 2004 (I ...
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Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono, "AC IO Loopback Design for High Speed uProcessor IO Test," Test Conference, International, pp. 23-30, International Test Conference 2004 (ITC'04), 2004.
 
 
BibTex
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@article{ 10.1109/ITC.2004.22,
author = {Benoit Provost and Chee How Lim and Mo Bashir and Ali Muhtaroglu and Tiffany Huang and Kathy Tian and Mubeen Atha and Cangsang Zhao and Harry Muljono},
title = {AC IO Loopback Design for High Speed uProcessor IO Test},
journal ={Test Conference, International},
volume = {0},
year = {2004},
issn = {1089-3539},
pages = {23-30},
doi = {http://doi.ieeecomputersociety.org/10.1109/ITC.2004.22},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Test Conference, International
TI - AC IO Loopback Design for High Speed uProcessor IO Test
SN - 1089-3539
SP23
EP30
A1 - Benoit Provost,
A1 - Chee How Lim,
A1 - Mo Bashir,
A1 - Ali Muhtaroglu,
A1 - Tiffany Huang,
A1 - Kathy Tian,
A1 - Mubeen Atha,
A1 - Cangsang Zhao,
A1 - Harry Muljono,
PY - 2004
KW - null
VL - 0
JA - Test Conference, International
ER -
 
Benoit Provost, Intel Corporation. Hillsboro, OR, USA
Chee How Lim, Intel Corporation. Hillsboro, OR, USA
Mo Bashir, Intel Corporation. Hillsboro, OR, USA
Ali Muhtaroglu, Intel Corporation. Hillsboro, OR, USA
Tiffany Huang, Intel Corporation. Santa Clara, CA, USA
Kathy Tian, Intel Corporation. Santa Clara, CA, USA
Mubeen Atha, Intel Corporation. Santa Clara, CA, USA
Cangsang Zhao, Intel Corporation. Santa Clara, CA, USA
Harry Muljono, Intel Corporation. Santa Clara, CA, USA
This paper presents the next generation AC IO Loopback design for two Intel processor architectures. Both designs detect I/O defects with 20 ps resolution and 50 ps jitter for up to 800 MHz bus speed. Even though the implementations differ in some aspects to accommodate two different bus architectures, the same prudent considerations for high speed operation, minimum test inaccuracy, and low implementation costs apply to both.
Citation:
Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono, "AC IO Loopback Design for High Speed uProcessor IO Test," itc, pp.23-30, International Test Conference 2004 (ITC'04), 2004
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