Reducing test application time and test data volume are major challenges in SoC design. In the case of IP cores, where no structural information is available, a common strategy is to compress the test data TD provided by the core vendor into an encoded format TE. Only the smaller set TE is stored on the ATE, and during test the original test data TD are regenerated by an on-chip decompressor. However, most of the encoding schemes suffer from two major drawbacks: Firstly, the irregularity of the encoded test data requires a complex test control including a handshake between the ATE and the system under test. Secondly, compression and decompression is very efficient for circuits with a single scan chain, however the extension to multiple scan chains requires either a separate decompressor for each chain or a serialization of the test data. So far, only a few approaches have been proposed trying to overcome these problems. Instead of dealing with the test vectors these approaches work with the slices to be fed into the scan chains, but they still allow a considerable degree of irregularity in the test application process. In this paper we propose a new dictionary based compression scheme which allows a fully regular test application while keeping the storage requirements low. Due to the regularity of the scheme the advantages of a multiple-scan architecture are preserved, and very low test times can be achieved.