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Defect Coverage Analysis of Partitioned Testing
Charlotte, NC, USA October 26-October 28
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ITC.2004.56International Test Conference 2004 (I ...
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Sreejit Chakravarty, Intel Corporation, Santa Clara, USA
Eric W Savage, Intel Corporation, Santa Clara, USA
Eric N Tran, Intel Corporation, Santa Clara, USA

Research in improving test quality has focused on identifying better fault models and coverage metrics and tools to achieve high coverage. The test generation and test application methodology is usually not considered. We attempt to understand the implication of a test generation and test application methodology, viz. partitioned testing, on product quality. In partitioned testing, patterns are applied to one part of the design while the other parts are maintained in a quiescent state.

Quantitative data on several aspects of partitioned testing, using some industrial test cases, are presented. It highlights the need for generating patterns using different partition sizes, generating longer test sequences and the need to include functional testing in the test suite. In addition, we argue that a different metric is needed to evaluate functional pattern quality to cover the gaps identified.

Citation:
Sreejit Chakravarty, Eric W Savage, Eric N Tran, "Defect Coverage Analysis of Partitioned Testing," itc, pp.907-915, International Test Conference 2004 (ITC'04), 2004
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