The Tester-Related Simulation Environment (TRSE) and applied methodology close the gap between physical test and simulation. Simulation checks the correctness of the implementation with respect to the specification, and test checks the correctness of the fabricated product with respect to the implementation. Unfortunately, simulation and test are still not connected in a smooth verification flow. Test cases and stimuli from simulation cannot be directly used for test. They may be used only in a restricted way, and after some adaptation. The approach presented here allows a better reuse of simulation stimuli for test issues. The main idea consists of inserting a special simulation element (SE) called a ?transforming SE?. This transforming SE is responsible for the adaptation and single cycle relation of the pattern. It also traces the interface pattern for direct use on a tester. These patterns are finally used for deriving test programs from functional patterns and for providing patterns for an e-beam analysis of the manufactured chip. The second main feature of the TRSE is the connection of each SE with an appropriate reference clock. This enables the SE to provide both synchronous and asynchronous communication with the unit under verification (UUV). Both the modeling of a test case and general methodology issues have a big influence in how easily a pattern can be adapted for the tester. Some practical modeling and methodology hints are given.