A Compact Piplined Hardware Implementation of the AES-128 Cipher

Las Vegas, Nevada April 10-April 12

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/ITNG.2006.1

Third International Conference on Inf ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Nadia Nedjah Articles by Luiza de Macedo Mourelle Articles by Marco Paulo Cardoso

	ASCII Text	x
	Nadia Nedjah, Luiza de Macedo Mourelle, Marco Paulo Cardoso, "A Compact Piplined Hardware Implementation of the AES-128 Cipher," Information Technology: New Generations, Third International Conference on, pp. 216-221, Third International Conference on Information Technology: New Generations (ITNG'06), 2006.

	BibTex	x
	@article{ 10.1109/ITNG.2006.1, author = {Nadia Nedjah and Luiza de Macedo Mourelle and Marco Paulo Cardoso}, title = {A Compact Piplined Hardware Implementation of the AES-128 Cipher}, journal ={Information Technology: New Generations, Third International Conference on}, volume = {0}, year = {2006}, isbn = {0-7695-2497-4}, pages = {216-221}, doi = {http://doi.ieeecomputersociety.org/10.1109/ITNG.2006.1}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - Information Technology: New Generations, Third International Conference on TI - A Compact Piplined Hardware Implementation of the AES-128 Cipher SN - 0-7695-2497-4 SP216 EP221 A1 - Nadia Nedjah, A1 - Luiza de Macedo Mourelle, A1 - Marco Paulo Cardoso, PY - 2006 KW - null VL - 0 JA - Information Technology: New Generations, Third International Conference on ER -

Nadia Nedjah, State University of Rio de Janeiro

Luiza de Macedo Mourelle, State University of Rio de Janeiro

Marco Paulo Cardoso, State University of Rio de Janeiro

Advanced Encryption Standard ? AES is the new encryption standard. In this paper, we propose a very efficient pipelined hardware implementation of AES-128 cipher. It has a competitive throughput of more than 2Gbits per second. Besides, improving the encryption throughput, the pipeline can be taken advantage of if the number of rounds (currently 10) must increase for security reasons.

Citation:

Nadia Nedjah, Luiza de Macedo Mourelle, Marco Paulo Cardoso, "A Compact Piplined Hardware Implementation of the AES-128 Cipher," itng, pp.216-221, Third International Conference on Information Technology: New Generations (ITNG'06), 2006

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.