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Implementing DSP applications on heterogeneous targets using minimal size data buffers
Thessaloniki, GREECE June 19-June 21
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWRSP.1996.506801Seventh IEEE International Workshop o ...
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M. Ade, R. Lauwereins, J.A. Peperstrate, "Implementing DSP applications on heterogeneous targets using minimal size data buffers," Rapid System Prototyping, IEEE International Workshop on, pp. 166, Seventh IEEE International Workshop on Rapid System Prototyping (RSP'96), 1996.
 
 
BibTex
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@article{ 10.1109/IWRSP.1996.506801,
author = {M. Ade and R. Lauwereins and J.A. Peperstrate},
title = {Implementing DSP applications on heterogeneous targets using minimal size data buffers},
journal ={Rapid System Prototyping, IEEE International Workshop on},
volume = {0},
year = {1996},
issn = {1074-6005},
pages = {166},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWRSP.1996.506801},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - Rapid System Prototyping, IEEE International Workshop on
TI - Implementing DSP applications on heterogeneous targets using minimal size data buffers
SN - 1074-6005
SP
EP
A1 - M. Ade,
A1 - R. Lauwereins,
A1 - J.A. Peperstrate,
PY - 1996
KW - signal processing; logic CAD; software prototyping; synchronous data flow; deadlock free schedule; GRAPE; digital signal processing; arbitrary target architectures; Field Programmable Gate Arrays; heterogeneous targets; minimal size data buffers; DSP
VL - 0
JA - Rapid System Prototyping, IEEE International Workshop on
ER -
 
M. Ade, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
R. Lauwereins, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
J.A. Peperstrate, ESAT, Katholieke Univ., Leuven, Heverlee, Belgium
The paper presents an algorithm to determine the smallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the existence of a deadlock free schedule. The presented algorithm fits in the design flow of GRAPE, an environment for the emulation and implementation of digital signal processing (DSP) systems on arbitrary target architectures, consisting of programmable DSP processors and FPGAs. Reducing the size of data buffers is of high importance when the application will be mapped on Field Programmable Gate Arrays (FPGA), since register resources are rather scarce.
Index Terms:
signal processing; logic CAD; software prototyping; synchronous data flow; deadlock free schedule; GRAPE; digital signal processing; arbitrary target architectures; Field Programmable Gate Arrays; heterogeneous targets; minimal size data buffers; DSP
Citation:
M. Ade, R. Lauwereins, J.A. Peperstrate, "Implementing DSP applications on heterogeneous targets using minimal size data buffers," rsp, pp.166, Seventh IEEE International Workshop on Rapid System Prototyping (RSP'96), 1996
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