Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters

Calgary, Alberta, Canada June 30-July 02

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213018

The 3rd IEEE International Workshop o ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Magesh Sadasivam Articles by Sangjin Hong

	ASCII Text	x
	Magesh Sadasivam, Sangjin Hong, "Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters," System-on-Chip for Real-Time Applications, International Workshop on, pp. 116, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003.

	BibTex	x
	@article{ 10.1109/IWSOC.2003.1213018, author = {Magesh Sadasivam and Sangjin Hong}, title = {Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters}, journal ={System-on-Chip for Real-Time Applications, International Workshop on}, volume = {0}, year = {2003}, isbn = {0-7695-1944-X}, pages = {116}, doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213018}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System-on-Chip for Real-Time Applications, International Workshop on TI - Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters SN - 0-7695-1944-X SP EP A1 - Magesh Sadasivam, A1 - Sangjin Hong, PY - 2003 KW - null VL - 0 JA - System-on-Chip for Real-Time Applications, International Workshop on ER -

Magesh Sadasivam

Sangjin Hong, State University of New York at Stony Brook

This paper presents an application specific reconfigurable architecture based on coarse-grain FPGA for real-time parallel particle filters. The architecture consists of a set of heterogeneous arithmetic units and buffer banks, where their interconnections are reconfigurable at the hardware level. The proposed architecture separates fixed and reconfigurable units for high-throughput realization. We compare potential throughput of the design with that of commercial FPGAs and DSPs. The proposed architecture is implemented in 0.25 ?m CMOS process.

Citation:

Magesh Sadasivam, Sangjin Hong, "Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters," iwsoc, pp.116, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.