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A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems
Calgary, Alberta, Canada June 30-July 02
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213021The 3rd IEEE International Workshop o ...
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Shih-Chang Hsia, "A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems," System-on-Chip for Real-Time Applications, International Workshop on, pp. 130, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003.
 
 
BibTex
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@article{ 10.1109/IWSOC.2003.1213021,
author = {Shih-Chang Hsia},
title = {A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2003},
isbn = {0-7695-1944-X},
pages = {130},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213021},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems
SN - 0-7695-1944-X
SP
EP
A1 - Shih-Chang Hsia,
PY - 2003
KW - null
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -
 
Shih-Chang Hsia, University of Science and Technology, Kaohsiung 824, Taiwan, R.O.C.
Currently, a comparison function has been widely used for discrete signal processing. In this study, a novel comparison-cell is presented based on clocking concept. The advantages are that the circuit complexity can be largely reduced and the delay time becomes shorter. The prototype cell is designed for 4-bit comparison cell using Spice simulator. As comparisons with CMOS base, the complexity of proposed cell is reduced to one-third, and the circuit delay can be shortened to half. With a regular design, the prototype of 4?6 comparison circuit is implemented based on 4-bit basic cell. The chip core is about 0.9mm2 using UMC 0.5 um process.
Citation:
Shih-Chang Hsia, "A High Speed Multi -Input Comparator with Clocking-Charge Based for Low-Power Systems," iwsoc, pp.130, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003
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