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Symbolic Simulation as a Simplifying Strategy for SoC Verification
Calgary, Alberta, Canada June 30-July 02
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213066The 3rd IEEE International Workshop o ...
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Emil DUMITRESCU, Dominique BORRIONE, "Symbolic Simulation as a Simplifying Strategy for SoC Verification," System-on-Chip for Real-Time Applications, International Workshop on, pp. 378, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003.
 
 
BibTex
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@article{ 10.1109/IWSOC.2003.1213066,
author = {Emil DUMITRESCU and Dominique BORRIONE},
title = {Symbolic Simulation as a Simplifying Strategy for SoC Verification},
journal ={System-on-Chip for Real-Time Applications, International Workshop on},
volume = {0},
year = {2003},
isbn = {0-7695-1944-X},
pages = {378},
doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2003.1213066},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - System-on-Chip for Real-Time Applications, International Workshop on
TI - Symbolic Simulation as a Simplifying Strategy for SoC Verification
SN - 0-7695-1944-X
SP
EP
A1 - Emil DUMITRESCU,
A1 - Dominique BORRIONE,
PY - 2003
KW - null
VL - 0
JA - System-on-Chip for Real-Time Applications, International Workshop on
ER -
 
Emil DUMITRESCU, TIMA Laboratory, Grenoble, FRANCE
Dominique BORRIONE, TIMA Laboratory, Grenoble, FRANCE
The successful application of model-checking to industrial designs requires methods for reducing the complexity of the model. This paper presents an original strategy, for a wellidentified class of circuit behaviors; by running an appropriate symbolic simulation pattern before the actual proof of a temporal formula, an important FSM model simplification can be obtained. The actual model reduction step is formalized and illustrated. This method has been implemented within the CMU version of the SMV modelchecking tool and validated on a large industrial design.
Citation:
Emil DUMITRESCU, Dominique BORRIONE, "Symbolic Simulation as a Simplifying Strategy for SoC Verification," iwsoc, pp.378, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 2003
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