A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture

Banff, Alberta, Canada July 20-July 24

DOI Bookmark:

http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.22

Fifth International Workshop on Syste ...

	This Article
	PURCHASE ARTICLE: $19 PDF HTML IEEE Xplore Subscribers
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Syed Masood Ali Articles by Rabin Raut Articles by Mohamad Sawan

	ASCII Text	x
	Syed Masood Ali, Rabin Raut, Mohamad Sawan, "A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture," System-on-Chip for Real-Time Applications, International Workshop on, pp. 123-126, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005.

	BibTex	x
	@article{ 10.1109/IWSOC.2005.22, author = {Syed Masood Ali and Rabin Raut and Mohamad Sawan}, title = {A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture}, journal ={System-on-Chip for Real-Time Applications, International Workshop on}, volume = {0}, year = {2005}, isbn = {0-7695-2403-6}, pages = {123-126}, doi = {http://doi.ieeecomputersociety.org/10.1109/IWSOC.2005.22}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - System-on-Chip for Real-Time Applications, International Workshop on TI - A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture SN - 0-7695-2403-6 SP123 EP126 A1 - Syed Masood Ali, A1 - Rabin Raut, A1 - Mohamad Sawan, PY - 2005 KW - null VL - 0 JA - System-on-Chip for Real-Time Applications, International Workshop on ER -

Syed Masood Ali, Concordia University

Rabin Raut, Concordia University

Mohamad Sawan, Ecole Polytechnique Montreal

The thermometer code to binary code (TC-to-BC) decoder is found to be one of the major limitations for flash type ADCs to perform satisfactorily for ultra high speed operations with minimum power dissipation. The authors propose a solution based on current mode approach to implement a Neural Network based Parallel ADC-decoder that is suitable for both system-on-chip and off-chip applications. The successful implementation is being presented for a 6-bit, 2GHz, with less than 19mW average power dissipation. The design was simulated using Cadence Spectre in a standard TSMC 0.18um technology.

Citation:

Syed Masood Ali, Rabin Raut, Mohamad Sawan, "A Power Efficient Decoder for 2GHz, 6-bit CMOS Flash-ADC Architecture," iwsoc, pp.123-126, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.