Proactive Use of Shared L3 Caches to Enhance Cache Communications in Multi-Core Processors

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http://doi.ieeecomputersociety.org/10.1109/L-CA.2008.10

July-December 2008 (vol. 7 no. 2) pp. 57-60

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	Sevin Fide, Stephen Jenks, "Proactive Use of Shared L3 Caches to Enhance Cache Communications in Multi-Core Processors," IEEE Computer Architecture Letters, vol. 7, no. 2, pp. 57-60, July-December, 2008.

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	@article{ 10.1109/L-CA.2008.10, author = {Sevin Fide and Stephen Jenks}, title = {Proactive Use of Shared L3 Caches to Enhance Cache Communications in Multi-Core Processors}, journal ={IEEE Computer Architecture Letters}, volume = {7}, number = {2}, issn = {}, year = {2008}, pages = {57-60}, doi = {http://doi.ieeecomputersociety.org/10.1109/L-CA.2008.10}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - IEEE Computer Architecture Letters TI - Proactive Use of Shared L3 Caches to Enhance Cache Communications in Multi-Core Processors IS - 2 SN - SP57 EP60 EPD - 57-60 A1 - Sevin Fide, A1 - Stephen Jenks, PY - 2008 KW - Multi-core/single-chip multiprocessors KW - Support for multi-threaded execution VL - 7 JA - IEEE Computer Architecture Letters ER -

Sevin Fide, University of California, Irvine

Stephen Jenks, University of California, Irvine

The software and hardware techniques to exploit the potential of multi-core processors are falling behind, even though the number of cores and cache levels per chip is increasing rapidly. There is no explicit communications support available, and hence inter-core communications depend on cache coherence protocols, resulting in demand-based cache line transfers with their inherent latency and overhead. In this paper, we present Software Controlled Eviction (SCE) to improve the performance of multithreaded applications running on multi-core processors by moving shared data to shared cache levels before it is demanded from remote private caches. Simulation results show that SCE offers significant performance improvement (8-28%) and reduces L3 cache misses by 88-98%.

Index Terms:

Multi-core/single-chip multiprocessors, Support for multi-threaded execution

Citation:

Sevin Fide, Stephen Jenks, "Proactive Use of Shared L3 Caches to Enhance Cache Communications in Multi-Core Processors," IEEE Computer Architecture Letters, vol. 7, no. 2, pp. 57-60, July-Dec. 2008, doi:10.1109/L-CA.2008.10

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