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Logic Synthesis for Manufacturability
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.15May/June 2004 (vol. 21 no. 3) pp. 192-199
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Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli, "Logic Synthesis for Manufacturability," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 192-199, May/June, 2004.
 
 
BibTex
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@article{ 10.1109/MDT.2004.15,
author = {Alessandra Nardi and Alberto L. Sangiovanni-Vincentelli},
title = {Logic Synthesis for Manufacturability},
journal ={IEEE Design and Test of Computers},
volume = {21},
number = {3},
issn = {0740-7475},
year = {2004},
pages = {192-199},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.15},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - MGZN
JO - IEEE Design and Test of Computers
TI - Logic Synthesis for Manufacturability
IS - 3
SN - 0740-7475
SP192
EP199
EPD - 192-199
A1 - Alessandra Nardi,
A1 - Alberto L. Sangiovanni-Vincentelli,
PY - 2004
VL - 21
JA - IEEE Design and Test of Computers
ER -
 
Alessandra Nardi, University of California, Berkeley
Alberto L. Sangiovanni-Vincentelli, University of California, Berkeley
Typically, design optimization during synthesis is for area and/or performance, while optimization for yield occurs at the layout level. To obtain more effective yield improvement, this article proposes elevating the abstraction level for yield optimization by introducing an interesting approach to yield-driven logic synthesis.
Citation:
Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli, "Logic Synthesis for Manufacturability," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 192-199, May/June 2004, doi:10.1109/MDT.2004.15
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