SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure

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http://doi.ieeecomputersociety.org/10.1109/MDT.2004.19

May/June 2004 (vol. 21 no. 3) pp. 200-207

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	ASCII Text	x
	Samvel Shoukourian, Valery Vardanian, Yervant Zorian, "SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 200-207, May/June, 2004.

	BibTex	x
	@article{ 10.1109/MDT.2004.19, author = {Samvel Shoukourian and Valery Vardanian and Yervant Zorian}, title = {SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure}, journal ={IEEE Design and Test of Computers}, volume = {21}, number = {3}, issn = {0740-7475}, year = {2004}, pages = {200-207}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.19}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure IS - 3 SN - 0740-7475 SP200 EP207 EPD - 200-207 A1 - Samvel Shoukourian, A1 - Valery Vardanian, A1 - Yervant Zorian, PY - 2004 VL - 21 JA - IEEE Design and Test of Computers ER -

Samvel Shoukourian, Virage Logic

Valery Vardanian, Virage Logic

Yervant Zorian, Virage Logic

Today, embedded memories are the most important contributor to SoC yield. To maximize embedded-memory yield, advanced test and repair solutions must be an integral part of the memory block. This article analyzes factors that affect memory yield and presents advanced techniques for maximizing their positive impact.

Citation:

Samvel Shoukourian, Valery Vardanian, Yervant Zorian, "SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 200-207, May/June 2004, doi:10.1109/MDT.2004.19

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