Designing Fault-Tolerant Techniques for SRAM-Based FPGAs

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http://doi.ieeecomputersociety.org/10.1109/MDT.2004.85

November/December 2004 (vol. 21 no. 6) pp. 552-562

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	Fernanda Gusmao de Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis, "Designing Fault-Tolerant Techniques for SRAM-Based FPGAs," IEEE Design and Test of Computers, vol. 21, no. 6, pp. 552-562, November/December, 2004.

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	@article{ 10.1109/MDT.2004.85, author = {Fernanda Gusmao de Lima Kastensmidt and Gustavo Neuberger and Renato Fernandes Hentschke and Luigi Carro and Ricardo Reis}, title = {Designing Fault-Tolerant Techniques for SRAM-Based FPGAs}, journal ={IEEE Design and Test of Computers}, volume = {21}, number = {6}, issn = {0740-7475}, year = {2004}, pages = {552-562}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.85}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Designing Fault-Tolerant Techniques for SRAM-Based FPGAs IS - 6 SN - 0740-7475 SP552 EP562 EPD - 552-562 A1 - Fernanda Gusmao de Lima Kastensmidt, A1 - Gustavo Neuberger, A1 - Renato Fernandes Hentschke, A1 - Luigi Carro, A1 - Ricardo Reis, PY - 2004 VL - 21 JA - IEEE Design and Test of Computers ER -

Fernanda Gusmao de Lima Kastensmidt, State University of Rio Grande do Sul

Gustavo Neuberger, Federal University of Rio Grande do Sul

Renato Fernandes Hentschke, Federal University of Rio Grande do Sul

Luigi Carro, Federal University of Rio Grande do Sul

Ricardo Reis, Federal University of Rio Grande do Sul

Editors' note: FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit's operation. This article presents a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CED) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques. —Dimitris Gizopoulos, University of Piraeus; and Yervant Zorian, Virage Logic

Citation:

Fernanda Gusmao de Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis, "Designing Fault-Tolerant Techniques for SRAM-Based FPGAs," IEEE Design and Test of Computers, vol. 21, no. 6, pp. 552-562, Nov./Dec. 2004, doi:10.1109/MDT.2004.85

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