Design, Synthesis, and Test of Networks on Chips

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http://doi.ieeecomputersociety.org/10.1109/MDT.2005.108

September/October 2005 (vol. 22 no. 5) pp. 404-413

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	ASCII Text	x
	Partha Pratim Pande, Cristian Grecu, Andr? Ivanov, Resve Saleh, Giovanni De Micheli, "Design, Synthesis, and Test of Networks on Chips," IEEE Design and Test of Computers, vol. 22, no. 5, pp. 404-413, September/October, 2005.

	BibTex	x
	@article{ 10.1109/MDT.2005.108, author = {Partha Pratim Pande and Cristian Grecu and Andr? Ivanov and Resve Saleh and Giovanni De Micheli}, title = {Design, Synthesis, and Test of Networks on Chips}, journal ={IEEE Design and Test of Computers}, volume = {22}, number = {5}, issn = {0740-7475}, year = {2005}, pages = {404-413}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.108}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Design, Synthesis, and Test of Networks on Chips IS - 5 SN - 0740-7475 SP404 EP413 EPD - 404-413 A1 - Partha Pratim Pande, A1 - Cristian Grecu, A1 - Andr? Ivanov, A1 - Resve Saleh, A1 - Giovanni De Micheli, PY - 2005 KW - VLSI KW - VLSI Systems KW - Automatic synthesis KW - Reliability KW - Testing KW - and Fault-Tolerance VL - 22 JA - IEEE Design and Test of Computers ER -

Partha Pratim Pande, Washington State University

Cristian Grecu, University of British Columbia

Andr? Ivanov, University of British Columbia

Resve Saleh, University of British Columbia

Giovanni De Micheli, Ecole Polytechnique Federale de Lausanne

For networks on chips to succeed as the next generation of on-chip interconnect, researchers must solve the major problems involved in designing, implementing, verifying, and testing them. This article surveys the latest NoC architectures, methods, and tools and shows what must happen to make NoCs part of a viable future.

Index Terms:

VLSI, VLSI Systems, Automatic synthesis, Reliability, Testing, and Fault-Tolerance

Citation:

Partha Pratim Pande, Cristian Grecu, Andr? Ivanov, Resve Saleh, Giovanni De Micheli, "Design, Synthesis, and Test of Networks on Chips," IEEE Design and Test of Computers, vol. 22, no. 5, pp. 404-413, Sep./Oct. 2005, doi:10.1109/MDT.2005.108

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