An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories

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http://doi.ieeecomputersociety.org/10.1109/MDT.2005.2

January/February 2005 (vol. 22 no. 1) pp. 50-58

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	Gustavo Neuberger, Fernanda Gusmao de Lima Kastensmidt, Ricardo Reis, "An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories," IEEE Design and Test of Computers, vol. 22, no. 1, pp. 50-58, January/February, 2005.

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	@article{ 10.1109/MDT.2005.2, author = {Gustavo Neuberger and Fernanda Gusmao de Lima Kastensmidt and Ricardo Reis}, title = {An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories}, journal ={IEEE Design and Test of Computers}, volume = {22}, number = {1}, issn = {0740-7475}, year = {2005}, pages = {50-58}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.2}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories IS - 1 SN - 0740-7475 SP50 EP58 EPD - 50-58 A1 - Gustavo Neuberger, A1 - Fernanda Gusmao de Lima Kastensmidt, A1 - Ricardo Reis, PY - 2005 VL - 22 JA - IEEE Design and Test of Computers ER -

Gustavo Neuberger, Federal University of Rio Grande do Sul

Fernanda Gusmao de Lima Kastensmidt, Federal University of Rio Grande do Sul

Ricardo Reis, Federal University of Rio Grande do Sul

Editors' note: Modern SoC architectures manufactured at ever-decreasing geometries use multiple embedded memories. Error detection and correction codes are becoming increasingly important to improve the fault tolerance of embedded memories. This article focuses on automatically optimizing classical Reed-Solomon codes by selecting the appropriate code polynomial and set of used symbols.

—Dimitris Gizopoulos, University of Piraeus; and Yervant Zorian, Virage Logic

Citation:

Gustavo Neuberger, Fernanda Gusmao de Lima Kastensmidt, Ricardo Reis, "An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories," IEEE Design and Test of Computers, vol. 22, no. 1, pp. 50-58, Jan./Feb. 2005, doi:10.1109/MDT.2005.2

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