Value-Added Defect Testing Techniques

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http://doi.ieeecomputersociety.org/10.1109/MDT.2005.74

May/June 2005 (vol. 22 no. 3) pp. 224-231

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	ASCII Text	x
	Jay Jahangiri, David Abercrombie, "Value-Added Defect Testing Techniques," IEEE Design and Test of Computers, vol. 22, no. 3, pp. 224-231, May/June, 2005.

	BibTex	x
	@article{ 10.1109/MDT.2005.74, author = {Jay Jahangiri and David Abercrombie}, title = {Value-Added Defect Testing Techniques}, journal ={IEEE Design and Test of Computers}, volume = {22}, number = {3}, issn = {0740-7475}, year = {2005}, pages = {224-231}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.74}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Value-Added Defect Testing Techniques IS - 3 SN - 0740-7475 SP224 EP231 EPD - 224-231 A1 - Jay Jahangiri, A1 - David Abercrombie, PY - 2005 KW - advanced design-for-manufacturability KW - DFM test methods KW - defect testing techniques VL - 22 JA - IEEE Design and Test of Computers ER -

Jay Jahangiri, Mentor Graphics

David Abercrombie, Mentor Graphics

This article describes advanced design-for-manufacturability (DFM) test methods that target defect coverage, yield learning, and cost. The authors argue that testing can be useful for more than filtering chips: It can directly help target test patterns, provide DFM tools, and reduce overall costs.

Index Terms:

advanced design-for-manufacturability, DFM test methods, defect testing techniques

Citation:

Jay Jahangiri, David Abercrombie, "Value-Added Defect Testing Techniques," IEEE Design and Test of Computers, vol. 22, no. 3, pp. 224-231, May/June 2005, doi:10.1109/MDT.2005.74

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