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A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.76July/August 2005 (vol. 22 no. 4) pp. 316-326
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Chen He, University of Texas at Austin and Freescale Semiconductor Inc.
Margarida F. Jacome, University of Texas at Austin
Gustavo de Veciana, University of Texas at Austin
To address the density, scalability, and reliability challenges of emerging nanotechnologies, the authors propose a hierarchy of design abstractions, constructed as reconfigurable fabric regions, whereby designers assign small functional flows to each region. The approach exposes a new class of yield, delay, and cost trade-offs that must be jointly considered when designing computing systems in defect-prone nanotechnologies.
Index Terms:
Nanotechnologies, probabilistic design, defect tolerance, reconfiguration
Citation:
Chen He, Margarida F. Jacome, Gustavo de Veciana, "A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 316-326, July/Aug. 2005, doi:10.1109/MDT.2005.76
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