Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics

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http://doi.ieeecomputersociety.org/10.1109/MDT.2005.97

July/August 2005 (vol. 22 no. 4) pp. 328-339

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	ASCII Text	x
	Jie Han, Jianbo Gao, Yan Qi, Pieter Jonker, Jos? A.B. Fortes, "Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 328-339, July/August, 2005.

	BibTex	x
	@article{ 10.1109/MDT.2005.97, author = {Jie Han and Jianbo Gao and Yan Qi and Pieter Jonker and Jos? A.B. Fortes}, title = {Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics}, journal ={IEEE Design and Test of Computers}, volume = {22}, number = {4}, issn = {0740-7475}, year = {2005}, pages = {328-339}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.97}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics IS - 4 SN - 0740-7475 SP328 EP339 EPD - 328-339 A1 - Jie Han, A1 - Jianbo Gao, A1 - Yan Qi, A1 - Pieter Jonker, A1 - Jos? A.B. Fortes, PY - 2005 KW - fault-tolerance KW - multiplexing KW - bifurcation analysis KW - error bounds KW - Markov chain KW - N-tuple modular redundancy (NMR) KW - interwoven redundant logic KW - random interwoven redundancy KW - nanoelectronics KW - nanotechnology VL - 22 JA - IEEE Design and Test of Computers ER -

Jie Han, University of Florida

Jianbo Gao, University of Florida

Yan Qi, Johns Hopkins University

Pieter Jonker, Delft University of Technology

Jos? A.B. Fortes, University of Florida

This article provides an overview of several logic redundancy schemes, including von Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant logic. The authors use Markov chain models and bifurcation analysis to compare the degree of redundancy and system reliability in these classical fault-tolerant approaches.

Index Terms:

fault-tolerance, multiplexing, bifurcation analysis, error bounds, Markov chain, N-tuple modular redundancy (NMR), interwoven redundant logic, random interwoven redundancy, nanoelectronics, nanotechnology

Citation:

Jie Han, Jianbo Gao, Yan Qi, Pieter Jonker, Jos? A.B. Fortes, "Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 328-339, July/Aug. 2005, doi:10.1109/MDT.2005.97

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