Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses

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http://doi.ieeecomputersociety.org/10.1109/MDT.2006.23

January/February 2006 (vol. 23 no. 1) pp. 46-57

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	David C. Keezer, Dany Minier, Patrice Ducharme, "Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses," IEEE Design and Test of Computers, vol. 23, no. 1, pp. 46-57, January/February, 2006.

	BibTex	x
	@article{ 10.1109/MDT.2006.23, author = {David C. Keezer and Dany Minier and Patrice Ducharme}, title = {Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses}, journal ={IEEE Design and Test of Computers}, volume = {23}, number = {1}, issn = {0740-7475}, year = {2006}, pages = {46-57}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2006.23}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses IS - 1 SN - 0740-7475 SP46 EP57 EPD - 46-57 A1 - David C. Keezer, A1 - Dany Minier, A1 - Patrice Ducharme, PY - 2006 KW - control structure reliability KW - testing KW - fault tolerance KW - multi-gigahertz testing KW - picosecond timing accuracy KW - jitter-tolerance testing KW - jitter injection VL - 23 JA - IEEE Design and Test of Computers ER -

David C. Keezer, Georgia Institute of Technology

Dany Minier, IBM Canada

Patrice Ducharme, IBM Canada

Editor's note: Source-synchronous I/O buses, such as PCI Express and HyperTransport, are difficult to test with synchronous ATE. This article describes source-synchronous driver and receiver test modules that are tailored for these buses and that have the additional advantage of supporting jitter injection.

--Scott Davidson, Sun Microsystems

Index Terms:

control structure reliability, testing, fault tolerance, multi-gigahertz testing, picosecond timing accuracy, jitter-tolerance testing, jitter injection

Citation:

David C. Keezer, Dany Minier, Patrice Ducharme, "Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses," IEEE Design and Test of Computers, vol. 23, no. 1, pp. 46-57, Jan./Feb. 2006, doi:10.1109/MDT.2006.23

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