VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG
|
This article describes a test compression technology, called VirtualScan, which achieves scan test cost reduction by inserting a small combinational broadcaster and compactor into the original circuit under test (CUT). In addition, one-pass ATPG takes into account all constraints imposed by the VirtualScan compression architecture, and generates compression test patterns in the same manner as a conventional full-scan ATPG. The simplicity of the combinational-logic-based compression technology further allows for flexibility in addressing unknown (X) values and fault-aliasing effects, through either an enhanced ATPG algorithm or enhanced compactor logic.
[1] 122 L.-T Wang, C.-W Wu, and X. Wen eds. , VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, 2006.
[2] International Technology Roadmap for Semiconductors, 2007, pp. 25-26, http://www.itrs.net/Links/2007ITRSExecSum2007.pdf .
[3] S. Kajihara, A. Murakami, and T. Kaneko, "On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits," Proc. 8th Asian Test Symp. (ATS 99), IEEE CS Press, 1999, pp. 20-24.
[4] X. Lin et al., "On Static Test Compaction and Test Pattern Ordering for Scan Designs," Proc. Int'l Test Conf. (ITC 01), IEEE CS Press, 2001, pp. 1088-1097.
[5] V. Jain and J. Waicukauski, "Scan Test Data Volume Reduction in Multi-clocked Designs with Safe Capture Technique," Proc. Int'l Test Conf. (ITC 02), IEEE CS Press, 2002, pp. 148-153.
[6] N.A. Touba, "Survey of Test Vector Compression Techniques," IEEE Design &Test, July-Aug. 2006, pp. 294-303.
[7] L.-T Wang et al., "VirtualScan: A New Compressed Scan Technology for Test Cost Reduction," Proc. Int'l Test Conf. (ITC 04), IEEE CS Press, 2004, pp. 916-925.
[8] Z. Wang et al., Compacting Test Responses Using X-Driven Compactor, US patent application 11/898,070, SynTest Technologies.
[9] N.A. Touba, "X-Canceling MISR: An X-Tolerant Methodology for Compacting Output Responses with Unknowns Using a MISR," Proc. Int'l Test Conf. (ITC 07), IEEE CS Press, no. 4437576, 2007, p. 10.
[10] S. Mitra and K. Kim, "X-Compact: An Efficient Response Compaction Technique," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Mar. 2004, pp. 421-432.
[11] W.-T Cheng et al., "Diagnose Compound Scan Chain and System Logic Defects," Proc. Int'l Test Conf. (ITC 07), IEEE CS Press, no. 4437578, 2007, p. 10.
[12] P. Girard, X. Wen, and N.A. Touba, "Low-Power Testing," System-on-Chip Test Architectures: Nanometer Design for Testability, L.-T Wang, C.E. Stroud, and N.A. Touba eds. Morgan Kaufmann, 2007, pp. 307-350.
Index Terms:
ATPG, scan testing, test compression, combinational broadcaster, combinational compactor, low-power testing, fault diagnosis
Citation:
Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu, "VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG," IEEE Design and Test of Computers, vol. 25, no. 2, pp. 122-130, Mar. 2008, doi:10.1109/MDT.2008.56
PURCHASE ARTICLE: $19
IEEE Xplore Subscribers
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb